Title :
An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme
Author :
Moon, B.-S. ; Chai, J.-W. ; Kim, J.-S. ; Yim, S.-M. ; Kim, S.-A. ; Kim, C. ; Cho, S.-I.
Author_Institution :
Memory Div., Samsung Electron., Kyungki, South Korea
Abstract :
An area-efficient packet-based 256 Mb DRAM with a 4 bank architecture and a peak bandwidth of 1.0 Gbps/pin at V/sub cc/=2.35 V, Temp=100/spl deg/C is developed. This chip features a daisy chained redundancy scheme, an area-efficient logic block placement and routing technique and a process insensitive DLL with duty error reduction scheme to overcome large chip size penalty and to improve chip yield.
Keywords :
DRAM chips; delay lock loops; integrated circuit yield; memory architecture; redundancy; 100 degC; 2 GB/s; 2.35 V; 256 Mbit; area-efficient logic block placement; chip size penalty; chip yield; daisy-chained redundancy scheme; duty error reduction scheme; four bank architecture; packet-based DRAM; peak bandwidth; process insensitive DLL; Abstracts; Cities and towns; Decoding; Degradation; Logic arrays; Moon; Random access memory; Redundancy; Routing; Switches;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934187
