A hardware-oriented design for weighted median filters

Author

Chen, Chun-Te ; Chen, Liang-Gee ; Hsiao, Jue-Hsuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

441

Lastpage

445

Abstract

In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design strategy, the proposed architecture can support not only weighted median filters but also rank order-based filters in high-speed applications

Keywords

circuit CAD; logic CAD; median filters; algorithm mapping; design consideration; hardware-oriented design; high throughput rate; multiple filtering inputs; rank order-based filters; weighted median filters; Adaptive filters; Algorithm design and analysis; Electronic mail; Image coding; Information filtering; Information filters; Noise reduction; Signal processing algorithms; Sorting; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486352

Filename

486352