DocumentCode
3248042
Title
Autonomous decentralized low-power system LSI using self-instructing predictive shutdown method
Author
Shimizu, T. ; Arakawa, F. ; Kawahara, T.
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fYear
2001
fDate
14-16 June 2001
Firstpage
55
Lastpage
56
Abstract
There is a strong demand from the mobile telecommunications industry for LSIs that achieve higher performance using less power. However, it is almost impossible in a short design period for a circuit designer to carry out an optimal design with both the power and performance items of a LSI having tens of millions of logic gates. Furthermore, a considerable component of the DC-leakage current originates from the subthreshold, gate leakage, and junction leakage currents of the MOS transistor even when the LSI is in an active state. This paper proposes an autonomous decentralized system LSI where each block has a predictive shutdown function using an MOS power switch controlled by a method based on self-instruction.
Keywords
digital integrated circuits; integrated circuit design; large scale integration; leakage currents; low-power electronics; power supply circuits; DC-leakage current; MOS power switch; autonomous decentralized system LSI; design period; gate leakage currents; junction leakage currents; logic gates; low-power system; mobile telecommunications industry; optimal design; self-instructing predictive shutdown method; subthreshold leakage currents; Clocks; Communication industry; Control systems; Energy consumption; Laboratories; Large scale integration; Leakage current; Power supplies; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934193
Filename
934193
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