ASIC design methodology with on-demand library generation

Author

Onodera, H. ; Hashimoto, M. ; Hashimoto, T.

Author_Institution

Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan

fYear

2001

fDate

14-16 June 2001

Firstpage

57

Lastpage

60

Abstract

This paper describes a custom design method of ASICs with on-demand library generation. According to the result of performance estimation, a tailored library is generated and supplied to cell-based design tools. A symbolic layout system that produces a cell layout with variable driving strength is developed. The tunability can be utilized for generating a rich set of driving strength as well as design optimization in post-layout stage. Design experiments and measured performance of a fabricated chip demonstrate the effectiveness of the proposed approach.

Keywords

application specific integrated circuits; cellular arrays; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; logic gates; software libraries; symbol manipulation; ASIC design methodology; cell-based design tools; custom design method; design optimization; on-demand library generation; performance estimation; post-layout stage; symbolic layout system; tailored library; variable driving strength; Application specific integrated circuits; Design engineering; Design methodology; Design optimization; Libraries; Logic design; Logic gates; Optimization methods; Semiconductor device measurement; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934194

Filename

934194