DocumentCode
3248074
Title
Combined Radix-10 and Radix-16 Division Unit
Author
Lang, Tomas ; Nannarelli, Alberto
Author_Institution
Univ. of California, Irvine
fYear
2007
fDate
4-7 Nov. 2007
Firstpage
967
Lastpage
971
Abstract
In this work we extend a previously proposed digit- recurrence radix-10 division unit to be able to perform also radix-16 division. The extension is simplified by the fact that in the radix-10 implementation the quotient digit is decomposed into two parts and that this decomposition is also appropriate for the radix-16 case. Moreover, to reduce the latency in the radix- 10 the most-significant portion of the datapath, including the selection function, has been implemented in radix-2, so that the modifications of that part to include radix-16 consists mainly in combining the two modules to obtain the selection constants. The rest of the modifications relate to the generation of multiples, to the carry-save adder, to the carry-propagate adder, and to the on-the-fly conversion and rounding. The implementation results show that the delay of an iteration is similar to that of the radix-10 case and that the area is about thirty percent larger.
Keywords
adders; carry logic; carry-propagate adder; carry-save adder; digit recurrence; radix-10 division unit; radix-16 division unit; selection function; Arithmetic; Computer science; Convergence; Delay; Diversity reception; Hardware; Informatics; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
978-1-4244-2109-1
Electronic_ISBN
1058-6393
Type
conf
DOI
10.1109/ACSSC.2007.4487363
Filename
4487363
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