Title :
Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/
Author :
Karnik, T. ; Bloechel, B. ; Soumyanath, K. ; De, V. ; Borkar, S.
Author_Institution :
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes an experiment to characterize soft error rate of static latches for neutrons using a neutron beam, with measured soft error rates as a function of diffusion collection areas and supply voltages. The paper also quantifies the effectiveness of two promising hardening techniques and scaling trends.
Keywords :
capacitance; cosmic ray interactions; flip-flops; integrated circuit reliability; integrated circuit testing; logic testing; neutron effects; radiation hardening (electronics); 0.18 micron; cosmic ray induced soft errors; diffusion collection areas; error rate; hardening techniques; neutron beam; scaling trends; static latches; Capacitance; Clocks; Cosmic rays; Error analysis; Microprocessors; Neutrons; Packaging; Particle beams; Testing; Voltage;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934195
