A solution for memory collision in semi-parallel FPGA-based LDPC decoder design

Author

Zarubica, Radivoje ; Wilson, Stephen G.

Author_Institution

Univ. of Virginia, Charlottesville

fYear

2007

fDate

4-7 Nov. 2007

Firstpage

982

Lastpage

986

Abstract

Low Density Parity Check (LDPC) decoders implementing long blocklength codes require semi-parallel design. One challenge when implementing these codes on Field Programmable Gate Arrays (FPGAs) is efficiently storing messages needed in the iteration process. To meet this challenge, a new class of LDPC codes is presented. They combine regularity of implementation with reduction of time needed for decoding process, and do not suffer of any significant performance loss due to their structure.

Keywords

decoding; field programmable gate arrays; parity check codes; blocklength codes; decoding process; field programmable gate arrays; iteration process; low density parity check decoders; memory collision; semiparallel FPGA-based LDPC decoder design; semiparallel design; Cities and towns; Code standards; Communication standards; Digital video broadcasting; Field programmable gate arrays; Iterative decoding; Message passing; Parity check codes; Performance loss; Sparse matrices;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-2109-1

Electronic_ISBN

1058-6393

Type

conf

DOI

10.1109/ACSSC.2007.4487366

Filename

4487366