Title :
A new column redundancy scheme for yield improvement of high speed DRAMs with multiple bit pre-fetch structure
Author :
Jae-Goo Lee ; Young-Hyun Jun ; Kye-Hyun Kyung ; Changsik Yoo ; Yong-Ho Cho ; Soo-In Cho
Author_Institution :
Memory Technol. & Product Div., Samsung Electron. Co. Ltd., Kyunggi, South Korea
Abstract :
A novel dual CSL column redundancy scheme (DCCR) that can improve effectiveness of repair and minimize overhead of die area is proposed. DCCR can repair failure bits of self-half I/O block by the unit of single bit, not by CSL. DCCR can also improve the data access speed by reducing the local I/O loading.
Keywords :
DRAM chips; cellular arrays; failure analysis; high-speed integrated circuits; integrated circuit reliability; integrated circuit yield; redundancy; column line selection; column redundancy scheme; data access speed; die area; dual CSL column redundancy scheme; failure bits; high speed DRAMs; local I/O loading; multiple bit pre-fetch structure; overhead; repair effectiveness; self-half I/O block; yield improvement; Costs; Fabrication; Fuses; Joining processes; Large-scale systems; Optical control; Production; Random access memory; Switches; Switching circuits;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934198
