DocumentCode :
3248163
Title :
Search space reduction in high level synthesis by use of an initial circuit
Author :
Masuda, Atsushi ; Imai, Hiroshi ; Hansen, Jeffery P. ; Sekine, Masatoshi
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
fYear :
1995
fDate :
29 Aug-1 Sep 1995
Firstpage :
471
Lastpage :
477
Abstract :
Most existing high-level synthesis (HLS) systems attempt to generate a circuit from a behavioral description “out of the void”, using the entire design space as the search domain. Because of the vastness of the search space, it is impossible to do more than a coarse grain search, often resulting in inefficient designs. This approach ignores the designer´s knowledge of the general structure of the circuit to be synthesized. In this paper, we describe the HLS system SIDER (Synthesis by Initial Design Extension and Refinement). SIDER utilizes designer knowledge about the design space in the form of an initial circuit. By limiting search to the neighborhood of this initial circuit, much finer grain search can be performed yielding a higher quality design. The effectiveness of the SIDER approach is shown by HLS of a 300 line C description of 27 instructions from a MC6502 CPU
Keywords :
high level synthesis; logic design; search problems; SIDER; Synthesis by Initial Design Extension and Refinement; finer grain search; high level synthesis; initial circuit; search space reduction; Central Processing Unit; Circuit synthesis; Cost function; Flow graphs; High level synthesis; Scheduling algorithm; Synthesizers; Tree data structures; Tree graphs; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
Type :
conf
DOI :
10.1109/ASPDAC.1995.486358
Filename :
486358
Link To Document :
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