Title :
A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit
Author :
Yamaoka, M. ; Yanagisawa, K. ; Shukuri, S. ; Norisue, K. ; Ishibashi, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A new memory redundancy technique using ie-flash (inverse-gate-electrode flash) memory cells was developed. Ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary to use it in system LSIs, and it can be programmed by logic tester. This new redundancy technique was successfully implemented in the cache memories of a 32-bit RISC microprocessor.
Keywords :
CMOS digital integrated circuits; cache storage; flash memories; large scale integration; microprocessor chips; reduced instruction set computing; 32 bit; RISC microprocessor; cache memories; ie-flash; inverse-gate-electrode flash; logic CMOS process; memory cells; memory redundancy technique; system LSIs; CMOS logic circuits; CMOS process; Flash memory; Large scale integration; Logic testing; MOS devices; Microprocessors; Reduced instruction set computing; Voltage; Writing;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934199
