A submicron Bi-CMOS-DMOS process for 20-30 and 50 V applications

Author

Nezar, A. ; Ludikhuize, A.W. ; Brock, R. ; Nowlin, N.

Author_Institution

Adv. Technol. Dev., Philips Semicond., Albuquerque, NM, USA

fYear

1997

fDate

26-29 May 1997

Firstpage

333

Lastpage

336

Abstract

This paper describes a high voltage process using 0.8 μm technology for mixed signal applications. The technology allows the integration of high side 20, 30 and 50-V n-type LDMOS transistors and 50 V p-type LDMOS transistors along with dense logic/analog 5 V-CMOS and complementary low and high voltage bipolar transistors. Extended drain NMOS and PMOS transistors (ENMOS-EPMOS) whose safe operating areas exceed 50 V were also implemented. This technology is ideal for intelligent power application

Keywords

BiCMOS integrated circuits; integrated circuit technology; mixed analogue-digital integrated circuits; power integrated circuits; 0.8 micron; 20 to 30 V; 50 V; analog 5 V CMOS transistors; complementary bipolar transistors; dense logic; extended drain NMOS transistors; extended drain PMOS transistor; high voltage bipolar transistors; high voltage process; intelligent power application; low voltage bipolar transistors; mixed signal applications; n-type LDMOS transistors; p-type LDMOS transistors; safe operating areas; submicron BiCMOS-DMOS process; CMOS logic circuits; CMOS process; CMOS technology; Implants; Low voltage; MOS devices; MOSFETs; Medium voltage; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 1997. ISPSD '97., 1997 IEEE International Symposium on

Conference_Location

Weimar

ISSN

1063-6854

Print_ISBN

0-7803-3993-2

Type

conf

DOI

10.1109/ISPSD.1997.601509

Filename

601509