DocumentCode :
3248220
Title :
Synthesis-for-testability using transformations
Author :
Potkonjak, Miodrag ; Dey, Sujit ; Roy, Rabindra K.
Author_Institution :
NEC, Princeton, NJ, USA
fYear :
1995
fDate :
29 Aug-1 Sep 1995
Firstpage :
485
Lastpage :
490
Abstract :
We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. A two-stage objective function, that estimates the area and testability of the final implementation, and also captures enabling effects of the transformations, is developed. Optimization is done using a new randomized branch and bound steepest descent algorithm. Application of the transformation algorithm on several examples demonstrates significant simultaneous improvement in both area and testability of the final implementations
Keywords :
high level synthesis; logic design; logic testing; randomised algorithms; area; behavioral specification; high level synthesis; optimization; partial scan cost; randomized branch and bound steepest descent; synthesis-for-testability; testability; transformations; Automatic test pattern generation; Automatic testing; Circuit testing; High level synthesis; IIR filters; Process design; Registers; Sequential analysis; System testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
Type :
conf
DOI :
10.1109/ASPDAC.1995.486360
Filename :
486360
Link To Document :
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