Performance verification using PDL and constraint satisfaction

The performance description language PDL provides a compact notation for the specification of non-functional attributes of VLSI systems. This paper presents evaluation mechanisms which allow the designer to assert performance goals on PDL models of VLSI systems and determine if the constrained models are satisfiable. This is done by developing a PDL performance model and constructing a constraint satisfaction problem from the system of dependencies. This allows the designer to verify that an implementation of a VLSI system can satisfy all performance goals