An intelligent, self-deducing graphical register transfer interface based on a distributed constraint logic computation

We present a graphical capture tool for register transfer level modeling which is capable of deducing bus widths and other such undeclared circuit parameters with minimal user intervention. Known design parameters are self-propagated over the entire circuit, and can lead for example to all undeclared bus widths becoming automatically defined. This frees the designer from explicitly declaring those circuit features which the tool can deduce. Furthermore this provides fully generic n-bit m-input components, such as “wide flip-flops” having uncommitted width, at that point in the design cycle when such constructs are most needed. The novel use of constraints within individual model elements, together with a distributed constraint logic computation, provides the deductive mechanism. We describe the facility and examine its performance on a number of test cases