Title :
A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM
Author :
Miwa, T. ; Yamada, J. ; Koike, H. ; Nakura, T. ; Kobayashi, T. ; Kasai, N. ; Toyoshima, H.
Author_Institution :
Silicon Syst. Res. Lab., NEC Corp., Sagamihara, Japan
Abstract :
This paper describes two new circuit techniques for nonvolatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-/spl mu/m-design-rule four-metal-layer NV-SRAM cell occupies 9.7 /spl mu/m/sup 2/, that is the same area as a 0.25-/spl mu/m three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array to improve its nonvolatile retention characteristics. A 512 Kbit test macro has also been designed with only one percent area overhead from a conventional SRAM macro.
Keywords :
CMOS memory circuits; SRAM chips; ferroelectric capacitors; ferroelectric storage; 0.25 micron; 512 Kbit; CMOS process; HV/negative-voltage plate line driver; LV nonvolatile SRAM; back-up ferroelectric capacitors; circuit techniques; four-metal-layer NV-SRAM cell; high voltage plate line driver; low-voltage NV-SRAM; nonvolatile retention characteristics; reliability; Capacitors; Driver circuits; Electrodes; Ferroelectric materials; National electric code; Nonvolatile memory; Polarization; Random access memory; Voltage; Wiring;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934217
