DocumentCode :
3248560
Title :
A model of VHDL for the analysis, transformation, and optimization of digital system designs
Author :
Wilsey, Philip A. ; Benz, David M. ; Pandey, Sheetanshu L.
Author_Institution :
Comput. Archit. Des. Lab., Cincinnati Univ., OH, USA
fYear :
1995
fDate :
29 Aug-1 Sep 1995
Firstpage :
611
Lastpage :
616
Abstract :
Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize
Keywords :
formal languages; hardware description languages; rewriting systems; VHDL; digital system designs; dynamic semantics; formal models; formal semantic models; hardware description language; language constructs; rewriting algebra; static rewriting; Algebra; Buildings; Computer architecture; Costs; Design automation; Design optimization; Digital systems; Handicapped aids; Hardware design languages; Libraries;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
Type :
conf
DOI :
10.1109/ASPDAC.1995.486377
Filename :
486377
Link To Document :
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