Title :
An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications
Author :
Lee, M.-J.E. ; Dally, W.J. ; Poulton, J.W. ; Chiang, P. ; Greenwood, S.E.
Author_Institution :
Stanford Univ., CA, USA
Abstract :
A 4 Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24 /spl mu/m CMOS technology dissipates 84 mW and occupies 0.3 mm/sup 2/. The input signal is 2/spl times/oversampled by 8 offset-cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the data eye using a semi-digital dual delay-locked loop (DLL). The quiet-supply p-p jitter of the receive clock is 39 ps with 0.33 ps/mV supply sensitivity. It allows for plesiochronous clocking with a frequency tolerance of /spl plusmn/400 ppm. The worst case phase resolution is <20 ps.
Keywords :
CMOS integrated circuits; data communication equipment; delay lock loops; digital communication; mixed analogue-digital integrated circuits; synchronisation; timing; 0.24 micron; 4 Gbit/s; 84 mW; ASIC; CMOS technology; clock recovery circuit; data recovery circuit; delay-locked loop; offset-cancelled receive amplifier; phase controller; plesiochronous clocking; semi-digital dual DLL; serial link applications; Bandwidth; CMOS technology; Circuit noise; Clocks; Counting circuits; Decoding; Frequency; Phase control; Timing; Voting;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934223
