Title :
An SOI CMOS LVDS driver and receiver pair
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
Abstract :
A low-voltage differential signaling (LVDS) driver and receiver pair utilizing source-body-tied silicon-on-insulator CMOS transistors is shown to operate at 1 Gb/s data rates with zero bit error rate using a 2/sup 31/-1 pseudo-random bit sequence. For the driver, a level-shifter with gate voltage protection transitions from thin oxide core transistors to DGO output transistors was used. The receiver uses parallel PFET and NFET dual gate oxide transistors to enable common-mode input from 0-2.4 V.
Keywords :
CMOS integrated circuits; driver circuits; low-power electronics; mixed analogue-digital integrated circuits; receivers; silicon-on-insulator; 0 to 2.4 V; 1 Gbit/s; SOI CMOS LVDS; common-mode input; driver/receiver pair; dual gate oxide transistors; gate voltage protection transitions; low-voltage differential signaling; pseudo-random bit sequence; source-body-tied transistors; zero bit error rate; Bit error rate; Circuit testing; Differential amplifiers; Driver circuits; Feedback circuits; History; Protection; Signal design; Silicon on insulator technology; Voltage;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934224