Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation

Author

Miyama, M. ; Kamohara, S. ; Okuyama, K. ; Oji, Y.

Author_Institution

Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan

fYear

2001

fDate

14-16 June 2001

Firstpage

163

Lastpage

166

Abstract

To achieve high yield products without degrading the performance, it is important to optimize the device condition, considering the process variation. We present a model parameter extraction methodology to extract the process variation from the E-T (Electrical Test) data. We have estimated the parametric yield of a 0.20 /spl mu/m process SRAM test chip using Monte Carlo simulation and have obtained good agreement compared to measurement. We also performed device optimization using a critical path to improve the parametric yield.

Keywords

Monte Carlo methods; SRAM chips; circuit optimisation; circuit simulation; integrated circuit modelling; integrated circuit testing; integrated circuit yield; 0.20 micron; Monte Carlo simulation; SRAM test chip; circuit level device optimization; critical path; device condition; device optimization; electrical test data; model parameter extraction methodology; parametric yield enhancement system; process variation; statistical circuit simulation; Circuit optimization; Circuit simulation; Data mining; Fluctuations; Integrated circuit yield; MOSFET circuits; Optimization methods; Parameter extraction; Testing; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934227

Filename

934227