Title :
A floating-body charge monitor circuit for partially depleted SOI CMOS
Author :
Kuang, J.B. ; Saccamango, M.J. ; Ratanaphanyarat, S.
Author_Institution :
Adv. Server Dev., IBM Corp., Rochester, MN, USA
Abstract :
This paper presents a floating-body charge monitor technique, which does not require the use of body contacts. This technique improves the performance and timing robustness of MUX-type and SRAM bit line circuits on partially depleted (PD) SOI CMOS. It can also be used as a calibration tool for SOI device models by virtue of its direct body charge monitoring.
Keywords :
CMOS integrated circuits; SRAM chips; calibration; charge measurement; condition monitoring; electric charge; silicon-on-insulator; timing; MUX-type bit line circuits; SOI device models; SRAM bit line circuits; Si; calibration tool; direct body charge monitoring; floating-body charge monitor circuit; partially depleted SOI CMOS; timing robustness; Calibration; Circuits; Latches; Mirrors; Monitoring; Partial discharges; Pulse amplifiers; Random access memory; Semiconductor device modeling; Timing;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934228
