Title :
A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process
Author :
Krishnapura, N. ; Tsividis, Y.
Author_Institution :
Celight Inc., Springfield, NJ, USA
Abstract :
A 2/sup nd/ order low-pass log-domain filter is fabricated in a 0.25 /spl mu/m CMOS technology using enhanced lateral bipolar transistors. pMOS devices operating in accumulation are used for the integration capacitors. The filter when tuned to a bandwidth of 22 kHz, consumes 4.1 /spl mu/W from a 1.5 V supply and has an r.m.s. output noise of 0.25 nA. The filter´s SNR at 1% THD is 56.1 dB and its maximum S/(N+THD) is 44.9 dB. The chip occupies 0.085 mm/sup 2/.
Keywords :
CMOS analogue integrated circuits; active filters; low-pass filters; low-power electronics; 0.25 micron; 1.5 V; 22 kHz; 4.1 muW; 56.1 dB; CMOS process; accumulation-mode PMOS devices; enhanced lateral bipolar transistors; enhanced lateral p-n-p devices; integrated capacitors; micropower log-domain filter; second-order low-pass filter; Bipolar transistors; CMOS process; CMOS technology; Capacitors; Circuit noise; Low pass filters; MOS devices; MOSFETs; Photonic band gap; Signal to noise ratio;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934231
