Title :
A low-swing clock double-edge triggered flip-flop
Author :
Chulwoo Kim ; Sung-Mo Kang
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Champaign, IL, USA
Abstract :
A low-swing clock double-edge triggered flip-flop (LSDBF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduces conflicting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in a clock network.
Keywords :
CMOS logic circuits; flip-flops; low-power electronics; timing; clock network; double-edge triggered flip-flop; low-swing clock flip-flop; power consumption reduction; Capacitance; Clocks; Energy consumption; Flip-flops; Leakage current; MOSFETs; Power engineering and energy; Power engineering computing; Power supplies; Voltage;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934232
