On-die clock jitter detector for high speed microprocessors

Author

Kuppuswamy, R. ; Callahan, K. ; Keng Wong ; Ratchen, D. ; Taylor, G.

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2001

fDate

14-16 June 2001

Firstpage

187

Lastpage

190

Abstract

An on-die clock jitter detector has been designed for high speed microprocessor circuits and fabricated in 0.18 /spl mu/m CMOS technology. Variation of internal clock high/low time or period has been recorded. Innovative circuit techniques are used to provide fast initial DLL lock, adaptive filtering, granular jitter computation, and enhanced immunity to power-supply noise. It compares individual clock cycles to the average clock period, reporting the differences. The system has multiple output modes to allow more complete understanding of the jitter distribution and time dependence.

Keywords

CMOS digital integrated circuits; detector circuits; high-speed integrated circuits; microprocessor chips; timing jitter; 0.18 micron; CMOS technology; adaptive filtering; circuit techniques; fast initial DLL lock; granular jitter computation; high speed microprocessors; multiple output modes; on-die clock jitter detector; power-supply noise immunity; Circuits; Clocks; Delay lines; Detectors; Jitter; Microprocessors; Phase detection; Phase locked loops; Phased arrays; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934233

Filename

934233