Optimum simultaneous placement and binding for bit-slice architectures

Traditionally, the problems of binding and placement in the synthesis of digital circuits have been formulated and solved separately. However, placement and binding strongly interact and design decisions taken during these phases determine the interconnect structure. As feature sizes continue to decrease, the delay caused by signal propagation through interconnect more and more dominate the overall system performance. Hence, optimizing interconnect becomes increasingly important. In this paper, we propose for the first time an analytical approach to capture the placement and binding problems in a single, unified Mixed Integer Linear Programming (MILP) model which also allows minimizing the overall interconnect structure. Such a model can serve as a starting point for deriving efficient heuristics in that it captures all information required for a comprehensive analysis of the problem. The target architecture is a linear bit-slice datapath, however, the model can be easily extended to handle two-dimensional datapath models