DocumentCode
3249048
Title
A 12-bit mismatch-shaped pipeline A/D converter
Author
Shabra, A. ; Hae-Seung Lee
Author_Institution
MIT, Cambridge, MA, USA
fYear
2001
fDate
14-16 June 2001
Firstpage
211
Lastpage
214
Abstract
This paper presents pipeline A/D converters with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out-of-band. A 77 dB SFDR is achieved at an oversampling ratio of 4 and a sampling rate of 51 Msample/s, which is a 12 dB improvement compared to a converter with no mismatch shaping. These results were obtained from a test chip fabricated in a 0.35 /spl mu/m CMOS process.
Keywords
CMOS integrated circuits; analogue-digital conversion; integrated circuit noise; pipeline processing; 0.35 micron; 12 bit; CMOS process; linearity improvement; mismatch-shaped pipeline ADC; oversampling; pipeline A/D converter; Analog-digital conversion; Capacitors; Circuits; Digital-to-frequency converters; Frequency conversion; Linearity; Pipelines; Quantization; Sampling methods; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934242
Filename
934242
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