Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect

Author

Narendra, S. ; Tschanz, J. ; Keshavarzi, A. ; Borkar, S. ; De, V.

Author_Institution

Microprocessor Res. Lab., Intel Corp., Hillsboro, OR, USA

fYear

2001

fDate

14-16 June 2001

Firstpage

217

Lastpage

218

Abstract

History effect measurements on different circuits in a 150 nm SOI technology show no adverse impact on worst-case delay vs. leakage trade-offs. The performance advantage of SOI over bulk is shown to come mostly from capacitance reduction. Hence, it will diminish with technology scaling.

Keywords

capacitance; integrated circuit measurement; integrated circuit technology; leakage currents; silicon-on-insulator; switching; 150 nm; PD-SOI technology; SOI history effect; Si; bulk technology; capacitance reduction; comparative performance; history effect measurements; leakage power; partially-depleted SOI; switching power; technology scaling; worst-case delay; Capacitance; Delay effects; History; Microprocessors; Power measurement; Pulse measurements; Pulsed power supplies; Space vector pulse width modulation; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-014-3

Type

conf

DOI

10.1109/VLSIC.2001.934244

Filename

934244

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3249085