DocumentCode
3249094
Title
A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology
Author
Fuse, T. ; Kameyama, A. ; Ohta, M. ; Ohuchi, K.
Author_Institution
Corp. Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
fYear
2001
fDate
14-16 June 2001
Firstpage
219
Lastpage
220
Abstract
Describes a novel power-supply scheme suitable for 0.5V operating LSIs. The system contains the on-chip buck dc-dc converter with over-90% efficiency, 0.5V operating logic, 100MHz operating F/Fs with holding data in the stand-by mode, and the dual-rail level converter. The dc-dc converter TEG, fabricated using 0.35/spl mu/m multi-Vt SOI CMOS process, realized stable recovery characteristics and a final stage efficiency of 92% with 0.5V/10mW output.
Keywords
CMOS integrated circuits; DC-DC power convertors; large scale integration; low-power electronics; power supply circuits; silicon-on-insulator; 0.35 micron; 0.5 V; 10 mW; 100 MHz; 92 percent; dual-rail level converter; low power LSIs; multi-Vt SOI CMOS technology; on-chip buck dc-dc converter; power-supply scheme; recovery characteristics; stage efficiency; stand-by mode; Batteries; Breakdown voltage; CMOS technology; Clocks; DC-DC power converters; Inverters; Large scale integration; Operational amplifiers; Power generation; Regulators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934245
Filename
934245
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