DocumentCode
3249351
Title
A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy
Author
Kaneko, Mineo ; Miyauchi, Hiroyuki
Author_Institution
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
fYear
1995
fDate
29 Aug-1 Sep 1995
Firstpage
829
Lastpage
836
Abstract
A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme
Keywords
fault tolerant computing; logic design; redundancy; systolic arrays; communication links; fault tolerant systolic arrays; link complexity; multiplicated multiple modular redundancy; Arithmetic; Concurrent computing; Electronic mail; Error correction; Fault tolerance; Fault tolerant systems; Redundancy; Signal processing algorithms; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location
Chiba
Print_ISBN
4-930813-67-0
Type
conf
DOI
10.1109/ASPDAC.1995.486410
Filename
486410
Link To Document