Title :
14.4-GS/s, 5-bit, 50mW time-interleaved ADC with distributed track-and-hold and sampling instant synchronization for ADC-based SerDes
Author :
Tao Jiang ; Chiang, Patrick Y.
Author_Institution :
Qualcomm Inc., Raleigh, NC, USA
fDate :
March 30 2015-April 1 2015
Abstract :
A 14.4-GS/s 5-b ADC is designed in 40nm CMOS with eight time-interleaved channels of Flash/Successive-Approximation hybrid sub-ADCs each running at 1.6GS/s. A modified bootstrapped track-and-hold switch incorporates a global clock to synchronize the sampling instant of each individual sub-channel, therefore improving multi-phase alignment. Measurement results show that the ADC can achieve a peak SNDR of 26.5dB, consuming 49.4mW, leading to a FoM of 199fJ/conversion-step, in a core area less than 800μm by 500μm.
Keywords :
CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; signal sampling; 40nm CMOS; bootstrapped track-and-hold switch; distributed track-and-hold synchronization; flash hybrid sub ADC; multiphase alignment improvement; noise figure 26.5 dB; power 49.4 mW; sampling instant synchronization; successive-approximation hybrid sub ADC; time-interleaved ADC-based SerDes; time-interleaved channels; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delays; Synchronization; Transistors; ADC; SAR; time-interleaving; track and hold;
Conference_Titel :
Wireless Symposium (IWS), 2015 IEEE International
Conference_Location :
Shenzhen
DOI :
10.1109/IEEE-IWS.2015.7164567
