Hybrid MCM Implementation for FIR Filters in FPGA Devices

Author

Howard, Charles D. ; DeBrunner, Linda S. ; DeBrunner, Victor

Author_Institution

FAMU-FSU Coll. of Electr. & Comput. Eng., Tallahassee

fYear

2007

fDate

4-7 Nov. 2007

Firstpage

1422

Lastpage

1425

Abstract

Multiple Constant Multiplication (MCM) has been helpful in improving ASIC filter designs for years, but for FPGAs MCM does not always make the best use of resources. In particular, specialized embedded hardware modules intended to improve DSP circuits are not used. This paper will demonstrate that reserving a select set of coefficients from the MCM optimizations and implementing them with the available embedded hardware can reduce FPGA area utilization.

Keywords

FIR filters; field programmable gate arrays; ASIC filter design; FIR filter; FPGA devices; embedded hardware module; field programmable gate arrays; hybrid multiple constant multiplication; Adders; Application specific integrated circuits; Circuit testing; Design engineering; Design optimization; Digital signal processing; Educational institutions; Field programmable gate arrays; Finite impulse response filter; Hardware;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-2109-1

Electronic_ISBN

1058-6393

Type

conf

DOI

10.1109/ACSSC.2007.4487463

Filename

4487463

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3249931