High speed flash analog-to-digital converter

In this paper, we design a pipelined flash ADC to achieve high speed of 2 GHz in 0.18 mum CMOS technology using Cadence design tools. We design a high speed track and hold and a novel thermometer to binary encoder. We considered several approaches to design the track and hold circuit, such as buffered track and hold, switched capacitor track and hold, and single tail track and hold. These circuits are slower or have stability problems. We have used a current mode dual array track and hold, which is not only stable but also ensures good performance at 2 GHz. The thermometer to binary encoder can be designed using fat tree encoder, differential cascade voltage switch using pass gate encoder and ROM encoder with pass gates. We implement a novel encoder, which has advantages of high speed and hardware reduction over existing encoder circuits. A clocked DCVSPG XOR gate and a quantum voltage comparator are also used to improve the speed of the proposed flash ADC