DocumentCode
3250520
Title
Preparation of custom gate array silicon wafers to handle specific wafer size in metallization process
Author
Ghahghahi, Farshad ; Hoss, Paul-André
Author_Institution
Tandem Comput. Inc., Cupertino, CA, USA
fYear
1989
fDate
25-27 Sep 1989
Firstpage
336
Lastpage
343
Abstract
A wafer reduction sizing and backgrinding process has been developed to downsize larger wafers received from semiconductor vendors to 4-in. diameter and personalize them through Tandem´s prototype wafer Fab line. This process avoided the equipment changes necessary to convert to a 5- or 6-in. wafer line, yet made it possible to accept larger wafers from vendors. The wafer sizing and backside grinding processes have been in place at Tandem for two years at a yield of 98%. Process steps are described in detail
Keywords
elemental semiconductors; grinding; logic arrays; metallisation; semiconductor technology; silicon; 4 in.; Si wafers; Tandem; backgrinding process; backside grinding processes; custom gate array wafers; downsize larger wafers; equipment change avoidance; existing equipment compatibility; metallization process; process steps; prototype wafer Fab line; semiconductors; wafer reduction sizing; wafer size reduction; yield; Chip scale packaging; Flowcharts; Investments; Metallization; Physics computing; Process design; Protection; Prototypes; Resists; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Manufacturing Technology Symposium, 1989, Proceedings. Seventh IEEE/CHMT International
Conference_Location
San Francisco, CA
Type
conf
DOI
10.1109/EMTS.1989.69001
Filename
69001
Link To Document