A 0.9 V operation 2-transistor flash memory for embedded logic LSIs

Author

Takahashi, K. ; Doi, H. ; Tamura, N. ; Mimuro, K. ; Hashizume, T. ; Moriyama, Y. ; Okuda, Y.

Author_Institution

ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto, Japan

fYear

1999

fDate

14-16 June 1999

Firstpage

21

Lastpage

22

Abstract

A novel 2-transistor flash memory cell is proposed to meet the read performance of mask ROMs. A very low 0.9 V nonword-line-boosting read operation is successfully achieved by employing a novel 2-transistor channel F-N program and channel F-N erase NOR (2-Tr CCNOR) flash memory architecture. We realize a low power program/erase scheme and high reliability by utilizing hole-free channel F-N tunneling with a simple memory cell structure and process.

Keywords

embedded systems; flash memories; integrated circuit design; integrated circuit measurement; integrated circuit reliability; large scale integration; memory architecture; tunnelling; 0.9 V; channel F-N erase; channel F-N program; embedded logic LSIs; flash memory architecture; hole-free channel F-N tunneling; low power program/erase scheme; mask ROMs; memory cell process; memory cell structure; nonword-line-boosting read operation; read performance; reliability; two-transistor NOR flash memory architecture; two-transistor flash memory; Fabrication; Flash memory; Large scale integration; Logic; MOS devices; Memory architecture; Read only memory; Tunneling; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799320

Filename

799320