Title :
Slotted vias for dual damascene interconnects in 1 Gb DRAMs
Author :
Schnabel, R.F. ; Bronner, G. ; Clevenger, L. ; Dobuzinsky, D. ; Costrini, G. ; Filippi, R. ; Gambino, J. ; Hug, M. ; Iggulden, R. ; Lin, C. ; Muller, K.P. ; Mueller, G. ; Nuetzel, J. ; Radens, C. ; Weber, S. ; Zach, F.
Author_Institution :
Siemens Microelectron., USA
Abstract :
A novel interconnect scheme is presented which has been used to significantly reduce the chip size of an 1 Gb SDRAM chip. The key element is the use of slotted vias for low resistance horizontal interconnects. This allows us to combine low capacitance/high resistance lines with low resistance/high capacitance lines. The slotted vias are realized by a dual damascene integration scheme without adding an additional mask level or process cost, with excellent continuity yield and good electromigration performance.
Keywords :
DRAM chips; SRAM chips; capacitance; electric resistance; electromigration; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; 1 Gbit; DRAMs; SDRAM chip; chip size; continuity yield; dual damascene integration; dual damascene interconnects; electromigration performance; interconnect scheme; low capacitance/high resistance lines; low resistance horizontal interconnects; low resistance/high capacitance lines; mask level; process cost; slotted vias; Artificial intelligence; Capacitance; Delay; Integrated circuit interconnections; LAN interconnection; Metallization; Microelectronics; Random access memory; SDRAM; Wiring;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799331
