Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs

Recently, to realize a high performance deca-nano scaled MOSFET, we reported a new MOSFET fabrication process named the "2-step activation annealing process" (2-step AAP) (Goto et al, 1997), which forms extension junctions with low temperature annealing after activation annealing of gate and deep source/drain (S/D) regions and sidewall removal. This process can achieve high dopant activity in the gate and S/D and a shallow junction in the extension region without causing further thermal diffusion (TD). Using this process, a 50 nm pMOSFET with excellent short channel effect (SCE) immunity and a high drive current has been demonstrated. However, when considering a salicide process, 2-step AAP increases the process steps because additional sidewall (SW) is required before the salicide process. Moreover, the S/D region suffers damage from over-etching through two SW formations. In this work, to prevent these problems, we developed a Co salicide compatible 2-step activation annealing process (Co&2AAP).