A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

Author

Imai, K. ; Shishiguchi, S. ; Yamaguchi, K. ; Kimizuka, N. ; Onishi, H. ; Horiuchi, T.

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Sagamihara, Japan

fYear

1999

fDate

14-16 June 1999

Firstpage

51

Lastpage

52

Abstract

We have developed a novel technology for formation of source/drain regions in 0.13 /spl mu/m MOSFETs. A combination of low-energy arsenic (8 keV) implantation and assist-phosphorous implantation suppresses transient enchanted diffusion (TED) of boron, and this improves I/sub on/-I/sub off/ characteristics as well as V/sub th/ roll-off. Assisted by low-dose phosphorous implantation, this technology can minimize both junction-leakage current and gate-poly depletion. An I/sub dsat/ of an nMOSFET of 750 /spl mu/A//spl mu/m (with t/sub ox//sup inv/ of 3.3 nm at 1.5 V) was obtained.

Keywords

MOSFET; arsenic; electric current; elemental semiconductors; ion implantation; leakage currents; phosphorus; semiconductor device measurement; silicon; 0.13 micron; 1.5 V; 10 keV; 3.3 nm; 8 keV; B transient enchanted diffusion suppression; MOSFET; Si:As,P,B; arsenic/assist-phosphorus implantation; assist-phosphorous implantation; gate-poly depletion; junction-leakage current; low-dose phosphorous implantation; low-energy arsenic implantation; nMOSFET; on-current/off-current characteristics; saturation drain current; source/drain formation technology; source/drain regions; threshold voltage roll-off; Boron; CMOS technology; Implants; Indium; Laboratories; Leakage current; MOS devices; MOSFET circuits; National electric code; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799335

Filename

799335