Framework for design with LEON3 system and testing with SHA-1 algorithm

Author

Mohanty, Madhulika ; Deb, Deepanjana ; Konidala, Aravind ; Mishra, Ashish ; Kota, Solomon Raju

Author_Institution

Comput. Sci. Group, Birla Inst. of Technol. & Sci., Pilani, India

fYear

2011

fDate

26-28 Dec. 2011

Firstpage

1

Lastpage

4

Abstract

The performance of many frequently used, computationally extensive algorithms can be improved by implementing them in hardware. This paper presents a framework for interfacing IP cores for such algorithms with the LEON3 processor and integrating them with the open source GRLIB IP library. The framework has been implemented by designing an IP Core for SHA-1, which is a popular cryptographic hash function, and interfacing it with the AMBA Advanced Peripheral Bus of the LEON3 soft processor provided by GRLIB IP library. The entire framework has been tested on the Xilinx ML509-XUPV5 board.

Keywords

cryptography; microprocessor chips; peripheral interfaces; AMBA advanced peripheral bus; IP core; LEON3 processor; SHA-1 algorithm; Xilinx ML509-XUPV5 board; cryptographic hash function; open source GRLIB IP library; Computer architecture; Hardware; IP networks; Kernel; Libraries; Linux; System-on-a-chip; AMBA; LEON3; Operation Rescheduling; SHA-1;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication and Industrial Application (ICCIA), 2011 International Conference on

Conference_Location

Kolkata, West Bengal

Print_ISBN

978-1-4577-1915-8

Type

conf

DOI

10.1109/ICCIndA.2011.6146655

Filename

6146655