Low resistance Co-salicided 0.1 /spl mu/m CMOS technology using selective Si growth

A low resistance salicided 0.1 /spl mu/m CMOSFET has been developed with precisely controlled T-shaped gate and optimum gate structure for thick CoSi/sub 2/. Selective Si growth (SSG) using a SiO/sub 2/-SiN stacked sidewall with the exposed SiN top hill enables suppression of junction leakage for thick Co silicidation, to eliminate bridging between gate and source/drain (S/D), and to precisely control the extra gate length for T-shaped gates. Moreover, the nitrogen profile in the p/sup +/ gate is optimized to suppress gate depletion induced by the thick Co. Since a heavily nitrided gate oxide insulator and N implantation of the poly-Si surface can prevent gate-implanted B ions from being diffused into the substrate and into the CoSi/sub 2/ layer, an increase in the gate sheet resistance, B penetration, and gate depletion can be simultaneously resolved, and thus high performance 0.1 /spl mu/m CMOS can be achieved with gates of as low as 1.9 /spl Omega//sq. sheet resistance.