C-V and gate tunneling current characterization of ultra-thin gate oxide MOS (t/sub ox/=1.3-1.8 nm)

Author

Chang-Hoon Choi ; Jung-Suk Goo ; Tae-Young Oh ; Zhiping Yu ; Dutton, R.W. ; Bayoumi, A. ; Min Cao ; Voorde, P.V. ; Vook, D.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1999

fDate

14-16 June 1999

Firstpage

63

Lastpage

64

Abstract

Direct tunneling of ultra-thin gate oxides results in exponential increases in gate leakage current (Lo et al, 1997). Moreover, the loss of inversion charge due to the carrier quantization then becomes significant. Hence, more physically accurate models are urgently needed. In this paper, an equivalent circuit approach considering the gate tunneling current as well as other QM effects is presented to characterize these phenomena for gate oxide thicknesses ranging from 1.3-1.8 nm.

Keywords

CMOS integrated circuits; dielectric thin films; equivalent circuits; integrated circuit measurement; integrated circuit modelling; leakage currents; quantum interference phenomena; tunnelling; 1.3 to 1.8 nm; C-V characterization; CMOS technology; QM effects; SiO/sub 2/-Si; carrier quantization; direct tunneling; equivalent circuit approach; gate leakage current; gate oxide thickness; gate tunneling current; gate tunneling current characterization; inversion charge loss; physically accurate models; ultra-thin gate oxide MOS; ultra-thin gate oxides; Capacitance; Capacitance-voltage characteristics; Circuit simulation; Electrical resistance measurement; Equivalent circuits; MOS capacitors; Semiconductor device modeling; Semiconductor process modeling; Thickness measurement; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799341

Filename

799341