A sub-1µA improved-transient CMOS low-dropout regulator without minimal ESR requirement

An ultra low-power CMOS low-dropout regulator (LDO), consuming only 680-nA quiescent current with fast transient response and 10-mA load capability, is proposed in this paper. It is designed in a 0.35-μm CMOS technology and verified by HSPICE simulations. With the proposed internal frequency compensation method, the LDO can be stabilized without minimal requirement of equivalent-series-resistance (ESR). This reduces the required PCB area and the component cost. In addition, the output ripple can be reduced due to the small ESR of the ceramic output capacitor. An adaptive current-boosting voltage buffer is used to improve the transient response. The response time of the proposed LDO is less than 2 μs when the load changes from 0.1 mA to 10 mA during 10 ns with a 1-μF ceramic output capacitor. The output voltage can recover to the nominal value within 50 μs, while the voltage spike is no more than 3 mV.