An efficient lateral channel profiling of poly-SiGe-gated PMOSFET´s for 0.1 /spl mu/m CMOS low-voltage applications

We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this scheme, the Ge fraction in the poly-SiGe gate was used to control threshold voltage V/sub T/, while short channel effects (SCE) were completely suppressed down to 100 nm gate lengths by heavily doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V/sub T/ roll-off behaviour, and 67 mV/dec sub-V/sub T/ voltage swing. The low channel doping leads to significant improvements in the channel mobility and parasitic capacitances, resulting in excellent I/sub on//I/sub off/ behaviour and record ring oscillator delays for low-voltage operation. Process variation analysis confirmed the high manufacturing potential for the approach suggested. The approach can be extended to n-type devices with a suitable choice of gate work function.