Title :
Design and implementation of PN sequence generator using Vedic multiplication
Author :
Jamgade, Roshni ; Ambatkar, Shrikant ; Kakde, Sandeep
Author_Institution :
Dept. of Electron. Eng., Yeshwantrao Chavan Coll. of Eng., Nagpur, India
Abstract :
In wide communication network, signals are transferred and receive. In case of wireless systems transferring a signal over a wide spectrum and providing a security to such signal is a tough task. While transferring a signal extra security is needed to hide the original message signal, to provide such security Pseudo Noise sequence is used. PN sequence uses linear feedback shift register (LFSR). A Vedic multiplier is an ancient method of mathematics using Vedic sutras. Uradhava triyakabham (vertically and crosswise) is one of the sutra used for design of fast and efficient multiplication. VHDL simulation of Vedic multiplier is done.
Keywords :
circuit feedback; hardware description languages; pseudonoise codes; radio networks; random sequences; shift registers; telecommunication security; LFSR; PN sequence generator implementation; VHDL simulation; Vedic multiplier; Vedic sutras; linear feedback shift register; pseudonoise sequence; signal security; wide communication network; wireless system; Algorithm design and analysis; Computer architecture; Convolution; Delays; Mathematical model; Simulation; Array multiplier; PN sequence; Uradhava triyakbhyam sutra; VHDL; Vedic mathematics;
Conference_Titel :
Computer Engineering and Applications (ICACEA), 2015 International Conference on Advances in
Conference_Location :
Ghaziabad
DOI :
10.1109/ICACEA.2015.7164651
