DocumentCode :
3251539
Title :
10-transistor 1-bit adders for n-bit parallel adders
Author :
Vasefi, Fartash ; Abid, Z.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Western Ontario, London, Ont., Canada
fYear :
2004
fDate :
6-8 Dec. 2004
Firstpage :
174
Lastpage :
177
Abstract :
Two designs of 10-transistor 1-bit adder are described in this paper. The output voltages levels of these 1-bit adders have a maximum of one threshold voltage (VT) loss. This is an important property since previously described 10-transistor designs suffer from two-threshold voltage loss. This also allows the successful use of these designs in a 4-bit ripple carry adder (RCA) and a 12-bit carry select adder (CSA). This is the first time where both the 4-bit and the 12-bit adders operate properly while using a 10-transistors 1-bit adder. All these circuits are implemented and simulated in 0.18 μm CMOS technology using Cadence development tools. The average power dissipation and maximum time delay have been recorded.
Keywords :
CMOS logic circuits; MOSFET; adders; circuit simulation; delays; network synthesis; 0.18 micron; 10-transistor 1-bit adders; 12-bit carry select adder; 4-bit ripple carry adder; CMOS technology; Cadence tool; n-bit parallel adders; power dissipation; threshold voltage loss; time delay; Adders; Application software; CMOS technology; Circuit simulation; Delay effects; Energy consumption; MOSFETs; Power dissipation; Signal design; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN :
0-7803-8656-6
Type :
conf
DOI :
10.1109/ICM.2004.1434237
Filename :
1434237
Link To Document :
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