A combined oscillation, power supply current and IDDQ testing methodology for fault detection in floating gate input CMOS operational amplifier

A technique integrating the oscillation, power supply current and I_DDQ based testing of circuit under test (CUT) is presented. A CMOS operational amplifier with floating gate input transistors, designed for operation at ±2.5 V in 1.5 μm n-well CMOS process, is used as the CUT. The faults simulating possible short and open manufacturing defects are introduced using the fault injection transistors. The change in oscillation frequency, power supply current and quiescent current is observed for fault detection. Two op-amps have been designed, one with twenty two short faults and the other with a combination of five open and seven short faults. Twenty two short faults and twelve combined open and short faults (except two short faults) have been detected by the combined testing methodology.