A modified efficient reduced-sample-rate delta-sigma-pipeline ADC architecture

Author

Majidzadeh, V. ; Shoaei, O.

Author_Institution

Dept. of ECE, Tehran Univ.

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

527

Abstract

A modified reduced sample rate delta-sigma-pipeline analog to digital converter architecture suitable for operating at low over sampling ratios (OSRs) is presented. The main advantages of this topology are the reduced and simplified analog circuit requirements and unity gain signal transfer function (STF). System level simulations verify the usefulness of the proposed architecture and show that fully 14-bit resolution can be achieved with only OSR of 4 and modulator order of two. Based on this architecture a single amplifier approach which needs a smaller chip area and power is used to realize the circuit implementation

Keywords

analogue-digital conversion; delta-sigma modulation; transfer functions; analog circuit requirements; analog to digital converter; delta-sigma-pipeline ADC architecture; over sampling ratio; reduced-sample-rate ADC architecture; signal transfer function; Analog integrated circuits; Analog-digital conversion; Circuit topology; Digital integrated circuits; Filters; Multi-stage noise shaping; Sampling methods; Signal resolution; Signal to noise ratio; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594154

Filename

1594154