Title :
A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond
Author :
Horii, H. ; Byoung Taek Lee ; Han Jin Lim ; Suk Ho Joo ; Chang Seok Kang ; Cha Young Yoo ; Hong Bae Park ; Wan Don Kim ; Sang In Lee ; Moon Yong Lee
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin, South Korea
Abstract :
We first developed a novel self-aligned electroplating process to fabricate Pt electrodes for integrated high-dielectric capacitors. Electroplated Pt filled 120 nm-wide buried contact (BC) holes (aspect ratio 2:1). Pt pillars of 210 nm diameter and 650 nm height were successfully fabricated. The leakage current density of sputtered BST capacitors using electroplated bottom Pt was less than 200 nA/cm/sup 2/ at /spl plusmn/1.5 V. The oxide-equivalent thickness T/sub oxeq/ and dissipation factor of 40 nm-thick BST films were 0.70 nm and 0.0080 at 0 V, respectively.
Keywords :
DRAM chips; MIS capacitors; barium compounds; current density; dielectric thin films; electrodes; electroplating; leakage currents; platinum; strontium compounds; 0.70 nm; 1 Gbit; 1.5 V; 120 nm; 210 nm; 40 nm; 650 nm; BST films; DRAMs; Pt electrodes; Pt electroplating method; Pt pillars; Pt-BaSrTiO/sub 3/; dissipation factor; electroplated Pt filled buried contact holes; electroplated bottom Pt; integrated high-dielectric capacitors; leakage current density; oxide-equivalent thickness; self-aligned electroplating process; self-aligned stacked capacitor; sputtered BST capacitors; Binary search trees; Capacitors; Dielectric materials; Electrodes; Leakage current; Random access memory; Sputter etching; Sputtering; Tin; Wet etching;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799361
