A programmable oversampling sigma-delta analog-to-digital converter

Author

Srivastava, Ashok ; Anantha, Raghavendra R.

Author_Institution

Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

539

Abstract

In this paper, an oversampling sigma-delta analog-to-digital converter (ADC) has been designed and implemented in 1.5 mum n-well CMOS process using a 1st order modulator and a 2nd order cascaded integrator comb (CIC) decimation filter. The modulator, which is the analog part of the ADC, has been designed using floating gate MOSFETs, which offers a higher common mode range for analog signals. The decimation filter is a digital low pass filter and can be programmed to give 7-bit and 10-bit digital outputs depending upon the oversampling ratio of 16 and 64, respectively. The ADC can be operated up to a clock sampling frequency of 8 MHz

Keywords

CMOS integrated circuits; MOSFET; comb filters; digital filters; integrated circuit design; low-pass filters; programmable circuits; sigma-delta modulation; 1.5 micron; 10 bit; 1st order modulator; 7 bit; 8 MHz; analog signals; cascaded integrator comb decimation filter; clock sampling frequency; digital low pass filter; floating gate MOSFET; n-well CMOS process; oversampling sigma-delta analog-to-digital converter; programmable sigma-delta analog-to-digital converter; Analog-digital conversion; CMOS process; Clocks; Delta-sigma modulation; Digital filters; Frequency; Low pass filters; MOSFETs; Sampling methods; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594157

Filename

1594157