Title :
A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI
Author :
Wakabayashi, H. ; Yamamoto, T. ; Saito, Y. ; Ogura, T. ; Narihiro, M. ; Tsuji, K. ; Fukai, T. ; Uejima, K. ; Nakahara, Y. ; Takeuchi, K. ; Ochiai, Y. ; Mogami, T. ; Kunio, T.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan
Abstract :
A 0.10 /spl mu/m CMOS device for system LSI was successfully integrated with a 40 nm gate sidewall (SW) using a local-channel structure, an offset spacer, highly-doped source/drain extensions (SDE), deep pocket implants, a shallow source/drain (S/D) with 7 /spl Omega///spl square/ CoSi/sub 2/ and four-level interconnects. Good drive current characteristics were observed as 618 and 295 /spl mu/A//spl mu/m at 1.5 V with lower off-currents of 0.75 and 0.22 nA//spl mu/m for n/pMOSFETs, respectively.
Keywords :
CMOS integrated circuits; MOSFET; doping profiles; electric current; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; ion implantation; large scale integration; 0.1 micron; 1.5 V; 40 nm; CMOS device; CoSi/sub 2/; deep pocket implants; drive current characteristics; four-level interconnects; gate sidewall; highly-doped source/drain extensions; local-channel structure; multilevel interconnects; nMOSFETs; off-currents; offset spacer; pMOSFETs; shallow source/drain; system LSI; Boron; Degradation; Etching; FETs; Laboratories; Large scale integration; MOSFETs; National electric code; Silicon; Temperature;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799363
