DocumentCode :
3251807
Title :
R-1 technology challenges for scaled Cu/low k interconnects
Author :
Kobayashi, Nao ; Havemann, R.
Author_Institution :
Hitachi
fYear :
1999
fDate :
14-16 June 1999
Firstpage :
113
Lastpage :
113
Abstract :
Summary form only given, as follows. Although copper interconnects have now been still unclear when comparing Cu with the more mature demonstrated on certain high performance products, AI technology. This session will address the technical significant technology challenges remain, including: Cu and strategic advantages and issues associated with the integration with low k dielectrics, scaling dual introduction of Cu/oxide and Cu/low k dielectrics with damascene structures and reliability of Cu/low k inter- the goal of highlighting industry needs and timeline for connects. In addition, the cost versus performance Cu technology insertion.
Keywords :
Artificial intelligence; Costs; Dielectric measurements; High K dielectric materials; High-K gate dielectrics; Monitoring; National electric code;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
Type :
conf
DOI :
10.1109/VLSIT.1999.799366
Filename :
799366
Link To Document :
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