Address code generation utilizing memory sharing in DSP processors

We propose an effective address code generation algorithm for digital signal processing (DSP) processors to minimize the size of addressing code. Unlike the traditional design flow in which the memory sharing for variables in code and the address (offset) assignment for the variables are performed sequentially without any interaction between them (mainly due to the high problem complexity to solve), our work attempts to tightly couple the memory sharing with offset assignment to exploit memory sharing on optimizing addressing instructions more effectively. We accomplish this by proposing a new integrated algorithm for memory sharing and address code generation that leads to efficient sequence of variable accesses, minimizing addressing instructions. Experimental results show average reduction of 10.8% in the address code size over that by the conventional approach